February 24, 2014
ECE Professor Andreas Veneris has been recognized with a Ten-Year Retrospective Most Influential Paper award for work published at IEEE’s Asian-South Pacific Design Automation Conference (ASP-DAC) in 2004. The paper, titled “Design Diagnosis Using Boolean Satisfiability” was co-authored with Alexander Smith and Anastasios Viglas.
Currently, the verification process occupies more than 70 per cent of the design cycle, with manual debugging responsible for least half of that effort. Professor Veneris’s paper in 2004 was the first to introduce automated debugging tools to the field of computer-aided design (CAD). Many research groups used the work to develop customized debugging frameworks, making the paper one of the most-cited papers in verification over the past decade.
“Our work provided the first formal theory and practical platform to tackle the debug bottleneck in verification,” said Professor Veneris.
ASP-DAC is the premiere event in the field of CAD for very-large-scale integration, or VLSI. The conference does not name a Ten-Year Retrospective winner every year, making this a particularly significant moment for Professor Veneris and his group.
“This award is an honour, and a recognition of the pioneering work by everybody in my group in the past 10 years that helped create awareness of the problem, but also developed practical solutions to address the growing debug pain,” he said.
Today, the Veneris group works on verification and debugging of system-level designs by incorporating for the first time formal and data mining techniques. More than 300 researchers, students and industry representatives attended this year’s ASP-DAC, which took place from January 20-23, 2014 in Singapore.
More information:
Marit Mitchell
Senior Communications Officer
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering
416-978-7997; marit.mitchell@utoronto.ca