Dr. Tony West, VP/CTO
Research & University Relations, Cisco Systems Inc.
The Winds of Change: How Technology Disruptions Drive the IT Industry – A Cisco Research Perspective
March 20, 2013 at 3:00 pm in HS-106 (Health Science Bldg, 155 College St.)
Abstract: Research partnerships between industry and academia are grown through relationships, a mutual desire for innovation, and opportunities for collaboration. IT is globalizing research relationships by reducing cycles times and the effects of geographic separation. From an industry perspective, innovation is driven by a need to develop competencies, “desirable” products, services, competitive markets and a dynamic talent pool. Cisco innovates through organic investment in in-house engineering, a hybrid combination of university partnerships, lectures, hosted sabbaticals, internships, fellowships, research awards, equipment donations, and corporate philanthropy – not to mention a strategy of innovation by company acquisition. This talk will outline Cisco’s approach to research and university recruitment (undergrads, grads, post-docs, and PIs), and hit on some of Cisco’s hot research “themes.” The talk should interest academic staff, researchers, and students.
Bio: Tony’s team works internally with Cisco’s technology leadership to understand forward strategy and technology needs, and externally with universities and other research institutions to look for capabilities and opportunities to create research partnerships. West has more than 35 years of innovation experience in the information technology industry, starting with research in local networks and protocols, to managing engineering teams developing network-based workstations and servers, to defining and managing IT and services architectures for large-scale global enterprises. West was VP/CTO for Global Services at Sun Microsystems, where he defined services technology for supporting an installed base of over 2 million installed customer systems, and led the way to a pre-emptive service model using network-based expert system technology. Prior to Sun, West worked in research at Xerox PARC and IBM Research. West holds a B.Sc. degree in Computing & Cybernetics from the University of Kent, UK, and a Ph.D. in Networking & Computer Science from Queen Mary College, London University, UK. In 2011, West was appointed Honorary Professor of Computing, Computing Laboratory, University of Kent, UK.
Paul E. McKenney, Ph.D.
IBM Distinguished Engineer, Linux Technology Center, IBM
Is Parallel Programming Hard, And If So, What Can You Do About It, Including Learning RCU?
Monday, November 5 — 11 am, BA 5205
Abstract: Parallel programming has earned a reputation of being extremely difficult. However, given the large quantity of production-quality parallel code being produced all around the world for a variety of open-source projects, it is worth asking whether this reputation is justified. Decades ago, parallelism’s bad reputation was in fact justified for the following reason: Parallel systems were rare and expensive. Very few people even had the chance to use parallel systems, let alone develop for them. There was almost no publicly available parallel code. Parallel engineering discipline was confined to a few companies creating proprietary parallel systems. Technological obstacles included synchronization overhead, deadlock, and data races.
But some things have changed dramatically over the past ten years. Parallel systems are now dirt cheap and readily available. As a result, almost anyone can now use and program parallel systems. Any number of open-source projects ranging from the Linux kernel to MariaDB to Samba support parallelism, and their code can be downloaded and studied by anyone with Internet access. These projects do their work in the open, so that successful parallel programming engineering disciplines can also be studied by anyone with Internet access.
Of course, some things have not changed. Despite all the progress over the past few decades, if you acquire locks out of order, you will still get a deadlock condition. However, engineering discipline, in other words, using the right tool for the job, can help you and your team avoid these pitfalls. This talk will give a brief overview of the technical and organizational measures you should take to successfully make use of parallelism.
Bio: Paul E. McKenney is an IBM Distinguished Engineer at the Linux Technology Center, where he maintains the RCU implementation within the Linux kernel, which serves workloads all the way from cellphones to supercomputers. Prior to that, he worked on the parallel DYNIX/ptx UNIX kernel at Sequent, and prior to that on packet-radio and Internet protocols (but long before it was polite to mention Internet at cocktail parties), system administration, business applications, and embedded/real-time systems.
Paul has recently returned to the embedded space, leading the IBM Linaro-consortium assignees. Now that multicore CPUs are appearing in many hand-held embedded devices, Paul is able to combine his parallel-programming and embedded experience, which is not something he would have guessed during his first stint with embedded in the early 1980s!
Paul received bachelors degrees in Computer Science and in Mechanical Engineering from Oregon State University in 1981, a masters degree in Computer Science from Oregon State University in 1988, as well as a Ph.D. in Computer Science and Engineering from Oregon Health and Sciences University in 2004. His Ph.D. topic? Why, RCU, of course!
Timothy O. (Tod) Dickson, Ph.D.
Research Staff Member, IBM T.J. Watson Research Center
Circuits and Architectures for Power-Efficient High-Speed Electrical I/O
September 6th, 10:30 am – 11:30 am, BA 1210
Abstract: Advances in digital computing capabilities create higher demands for serial data transmission. Sustaining these bandwidth demands requires innovations on several fronts. Future packaging technologies must enable ultra-dense chip-to-chip interconnects. This in turn creates a need for compact, power-efficient I/O with equalization capable of supporting multi-Gb/s communication over these interconnects. In this talk, solutions to enable future electrical I/O bandwidth demands will be presented. After a brief overview of equalization techniques, design examples of equalizing receivers in 45nm SOI CMOS technologies will be shown, focusing on low-power circuits and architectures. Additionally, a compact 8×10-Gb/s I/O subsystem mounted to a silicon interposer via 50mm pitch “micro-C4” bumps will be described.
The I/O includes a DFE-IIR equalizer in the receiver tailored for lossy silicon carrier interconnects, and bus-level redundancy that enables periodic recalibration of each serial link in a round-robin fashion. This work demonstrates the potential of silicon packaging technologies for achieving high bandwidth chip-to-chip communication by sending multi-Gb/s data over a large number of parallel interconnects, paving the way for increased module bandwidth for high-performance computing systems.
Bio: Timothy (Tod) Dickson received the B.S. and M.Eng. degrees in Electrical Engineering from the University of Florida, and the Ph.D. degree from the University of Toronto. Since 2006, he has been with the IBM T.J. Watson Research Center in Yorktown Heights, NY, where he is currently a Research Staff Member. His research focuses on the design of low-power multi-Gb/s serial I/O transceivers. He is also an Adjunct Assistant Professor at Columbia University in New York City, where he teaches graduate-level courses in analog and mixed-signal circuits and systems.
Dr. Dickson has been a recipient or co-recipient of several best paper awards, including the Best Paper Award for the 2009 IEEE Journal of Solid-State Circuits, the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the Best Student Paper Award at the 2004 Symposium on VLSI Circuits, and the Best Paper Award at the 2011 IEEE Conference on Electrical Performance of Electronic Packaging and Systems. He served as a member of the Technical Programming Committee of the IEEE Compound Semiconductor Integrated Circuit Symposium from 2007-2009, and was a guest editor of the October 2010 issue of the IEEE Journal of Solid-State Circuits.