Research Partnership Lectures

J. Thomas Pawlowski, Fellow and Chief Technologist, Micron Technology, Inc.

J. Thomas Pawlowski.‘A Vision of Future Processor/Memory Systems’
Wednesday, March 11, 2015 at 12:00 noon
Galbraith Building, room 119

Abstract: We stand at the most exciting time in the history of processor and memory development. Everyone can see the end of CMOS logic scaling, the only debate being at which node. The end of “Moore’s Law” is hotly debated and many intelligent discussions propose a different future direction for the industry at that point, whether or not in fact we have already seen this end. This talk presents a challenging and different perspective. We examine the reality of scaling in both CMOS and memory technologies. From this analysis new directions become apparent. What are the real walls? What products do we build as scaling challenges mount? What is the balance between use of CMOS and memory technologies as we further scale? Which technology does which kind of processing and movement of data? We will briefly discuss new Micron products which are inspired by the answers of these questions. We will examine the big picture: the future of processor/memory systems and the relationship between the two prime components. The necessity of memory abstraction will be demonstrated. New possibilities will be explored along with implications to the future of computing and the new building blocks we will need to make this future a reality.

Bio: J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Architecture Development Group. His responsibilities include evaluating new technologies and investments, exploring new memory and system architectures, and providing guidance to many technical teams, both internally and external to Micron. Mr. Pawlowski’s experience includes the creation or co-creation of numerous ground-breaking memory architectures and concepts including: synchronous burst pipelined SRAM; hierarchical cache systems; Zero Bus Turnaround SRAM; abstracted memory; the first double data rate memory (starting with SRAM and extending to DRAM and NAND technologies); Pseudo-Static RAM; high-speed NAND; the first double address rate memory; the first quad data rate memory; the first multi-channel memory; memories on SERDES buses; RLDRAM (the first DRAM to exceed SRAM performance); refresh and error correction schemes for memory subsystems; the first 3D memory concept; root hardware architecture of Micron’s newly announced nondeterministic Finite Automata Processor; and other projects still in development. Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada. He has well over 100 U.S. and in-flight patents and serves on several advisory boards and conference program committees. In his spare time, Mr. Pawlowski designs and builds loudspeakers, custom tools, and he has completed 63% of the design and fabrication of a revolutionary electric car concept.


Past Speakers

Dr. Gabriele Manganaro, Engineering Director, Analog Devices

Dr. Gabriele Manganaro.‘Data Converters for Wireless Infrastructure’
Wednesday, April 23, 2014 at 11:00 a.m.
Bahen Centre for Information Technology, Room 1170, 40 St. George Street, University of Toronto

Abstract: In recent years, a number of different technologies, including the introduction of smart phones, tablets, but also a variety of cloud-based services, have driven a steady increase of demand for faster and more pervasive personal mobile communication systems. New services and ever increasing number of mobile devices suggest that such growth trends are going to be well sustained for more years ahead. That has resulted into the introduction a growing variety of wireless base stations creating the connection points between the nearby mobile terminals and the main wired network. The RF/analog circuitry in wireless base stations has always been somewhat of a bottleneck in such systems. Data converters (ADCs and DACs) certainly are critical links of such signal processing chain. However, the nature, the technical and the cost tradeoffs involved in the design of data converters are changing dynamically as result of all that. The aim of this presentation is to illustrate how such changes are driving the design of ADCs and DACs and which architectures are emerging as result.

Bio: Gabriele Manganaro holds a D.Eng. and a Ph.D. in Electronics from the University of Catania, Italy. Starting in 1994, he did research with ST Microelectronics and Texas A&M University. He worked in data converters’ IC design at Texas Instruments, Engim Inc., and as Design Director at National Semiconductor. He is Engineering Director at Analog Devices. He was Associate Editor, then Deputy Editor in Chief and finally Editor in Chief for IEEE Trans. On Circuits and Systems – Part I.  He authored/co-authored 60 papers, three books, and holds 12 US patents. He is Senior Member IEEE and a Fellow of IET.

Bill Wallace and Roger Stancliff

New Microwave Measurements
Monday, Dec. 9, 2013 at 11:00 a.m.
Galbraith 221, 35 St. George Street, University of Toronto

Abstract: Traditionally, the microwave vector network analyzer has been used to characterize, model and measure electronic components for wireless devices, semiconductors and aerospace defense systems. More recently, new applications outside of these traditional electronic markets have begun to emerge. In this talk, we will briefly cover the history and current state of vector network analyzers. Then we will discuss the physics of microwave sensing: three words describe this (small, wet and changing). This physics of microwave interaction with materials lead to new applications in medical diagnostics, homeland security, process analytics and nanoscale device and material measurements. We will illustrate these new applications with numerous examples from research groups and start-up companies around the world.

Roger Stancliff, CTO, Agilent Component Test Division
Mr. Stancliff received his BSEE in 1972 and his MEE in 1973 from Cornell University in microwave electronics. He joined Hewlett Packard in 1973 as an R&D engineer to design microwave components for instrumentation. Since then he has held a variety of R&D and R&D management positions in HP and, since 1999, in HP’s spinout company Agilent Technologies in the areas of microwave signal generators, spectrum analyzers, and network analyzers. In 1994 he received his MS degree in the management of technology from NTU in the US. Most recently he was R&D manager, then Product Planning manager, and, since 2002, the CTO of the Component Test Division of Agilent. As CTO he led the development of the scanning microwave microscope and is currently focused on many different applications of microwave measurement outside of electronics. His present responsibilities include leading the development of new businesses and technologies and collaborating broadly with Universities, institutes, and companies to accomplish this.

Bill Wallace, Director, Americas University Business Development
Throughout his 29 year career with HP/Agilent, Bill has held a variety of roles including Global Account Manager for Texas Instruments and Hewlett Packard, a variety of  management and individual contributor roles in the mobile FM radio, Aerospace and Defense, Defense Electronics, High Energy Physics, Cell Phone Design, Cell Phone Manufacturing and InfoTech, Digital Design and Semiconductor market. Bill is a graduate of Texas A&M University and is currently on the Industry Advisory Board of Baylor Wireless and Microwave and Circuits and Systems (WMCS), the UC San Diego Department of Nano Engineering and the ECE Department at University of Texas at Arlington.

Dr. Tuyen Tran, Engineering Technology Development Manager

Intel, Portland Technology Development Division
‘Moore’s Law- Is There Still Plenty of Room at The Bottom?’
Thursday, Nov. 21, 2013 at 3:00pm
Sandford Fleming 1105, 10 King’s College Road, University of Toronto

Dr. Tran will discuss the history of transistor scaling at Intel, the future of Moore’s Law, as well as Intel’s research, development and manufacturing methodology and silicon technology leadership.  His presentation will address how Intel’s process technologies have evolved and include discussion on Intel’s latest iteration of silicon technology with 14nm Tri-Gate transistors.

Bio: Dr. Tuyen Tran is an Engineering Technology Development Manager with Intel’s Portland Technology Development (PTD) Division.  Since joining PTD in 1996, Dr. Tran has worked on a variety of technical projects in the development of Defect Inspection Technologies and Yield Improvement.  He is currently working on the research, development and integration of state of the art inspection, imaging, and elemental composition analysis capability for the 14nm and 10nm technologies.

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