Title: The Light at the End of the CMOS Tunnel
Date: September 15, 2011, 3 p.m. in SF1105
Abstract: In spite of numerous predictions to the contrary, Silicon technology is marching along past the 22nm node and on to ever finer dimensions. Innovations at the technology, device, circuit and system levels continue to enable us to scale in spite of what sometime appear to be insurmountable problems in power, lack of performance, manufacturability and so on. To a large degree, these innovations are necessary because no substitute technology has been found as yet and, in fact, it does not appear likely that any such technology will become practical this decade. This leaves us with the need to anticipate and predict the near and medium term futures of CMOS for the next handful of technology nodes. This talk will focus on doing just that, and will show how an important new constraint on future system scaling is circuit resilience.
Resilience is the ability of circuits to operate in spite of challenges like noise, difficult environmental conditions, aging and manufacturing imperfections. These factors conspire to cause transient or permanent errors that are indistinguishable from traditional “hard” faults typically caused by defects during fabrication. Without significant innovation at the circuit and system levels, the probability of these events can rise quite dramatically. In the area of SRAM, such phenomena have existed for the last three or four technology nodes, but significant investments in this area have indeed allowed continued system level scaling with ever larger on-chip memories. As these same phenomena start attacking integrated circuits more pervasively, there is an urgent need for research and development in this area to avert the problems certain to arise with increased defect rates.
To motivate such research, we will present a roadmap for predicting the resilience of CMOS circuits down to the 12nm node, and show examples of how innovations at the circuit and system levels can indeed be used to prolong the life of CMOS, and allow for system level operation in spite of frequent device level defects.
Bio: Sani received his Bachelors degree with Honors from the American University of Beirut in 1980, and his Masters and PhD degrees from Carnegie-Mellon University in 1981 and 1985 respectively. He then worked for ten years at Bell Laboratories in the general area of technology CAD, focusing on various aspects of design/technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. While at Bell Labs, working under Larry Nagel -the original author of Spice, he led a large team in the development of an in-house circuit simulator, named Celerity, which became the main circuit simulation tool at Bell Labs.
In January 1996, he joined the then newly formed IBM Austin Research Laboratory (ARL), which was founded with a specific focus on research for the support of computer systems. Sani currently manages the Silicon Analytics department at ARL , which is focused on applying analytics to the design/technology coupling area and includes activities in: model to hardware matching, simulation and modeling, statistical modeling, statistical technology characterization and similar areas.
Sani has authored numerous conference and journal publications, and delivered many tutorials at top conferences. He has received four Best Paper awards, authored invited papers to ISSCC, IEDM, ISLPED, HOTCHIPS, and CICC, given invited talks at Texas A&M University, RICE University, UCSB, UC Berkeley and Kyoto University. He has given Keynote and Plenary presentations at Sasimi, ESSCIRC/DERC, BMAS, SISPAD, SEMICON, PATMOS and ICCV. He is an IEEE Fellow, a member of the ACM and AAAS, and has a total of 44 patents. Sani is a member of the IBM Academy of Technology.
Dr. Nassif is currently serving as the Vice-President for Conferences of the IEEE council on EDA, and was the General chair of the ICCAD conference in 2008. He has previously also served on the technical program committees of DAC, ICCAD, DATE and ISQED, and on the executive committee of ISPD. He has received the Penrose award (given to one outstanding graduate from the American University of Beirut), the Distinguished Member of Technical Staff award from Bell Labs, two Research Accomplishment Awards from IBM, and the Mahboob-Khan Outstanding Mentor awards from the SRC.
Sani represents IBM as a member of the SRC Science Area Coordinating Committee for CAD and Test, and chaired the committee in 2006. He maintains strong ties with academia, and has participated in numerous PhD committees for students from MIT, CMU, Univ. Minnesota, Univ. Texas Austin, Texas A&M, UCSB, UCI, and Univ. Michigan.