Alain J. Martin

Knowledge is Power but Ignorance is Bliss: Theory and Methods for Asynchronous (QDI) Logic

Abstract: The use of a global clock to enforce sequencing in a VLSI implementation of a digital computation relies on a knowledge of timing (gate and wire delays) that constitutes both an advantage and a drawback. Its advantage is simplicity. But as continuing circuit miniaturization ("scaling'') makes this knowledge less and less precise, the drawbacks are starting to outweigh the advantages.

In this talk, Professor Martin will present an overview of asynchronous logic, a design approach for digital VLSI that does not use clock.  He will show that delay insensitivity---i.e. the complete ignorance of delays -- is impossible. Instead, he will introduce the concept of "quasi-delay-insensitivity'' (QDI), in which a minimal timing assumption, the "isochronic fork'' is sufficient for implementing any computation.  Martin will briefly describe the several asynchronous microprocessors designed at Caltech and will give evidence of the robustness and efficiency of QDI designs in the presence of large parameter variations.

Bio:  Alain J. Martin is a Professor of Computer Science at the California Institute of Technology. He is a graduate from the Institut National Polytechnique de Grenoble, France. His research interests include concurrent and distributed computing, asynchronous VLSI design, and computer architecture. His research group is well-known for their pioneering work in the area of asynchronous VLSI methodology and asynchronous microprocessor architectures. In 1988, they designed the world-first asynchronous microprocessor.